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cy62137fv18 mobl ? 2-mbit (128 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-08030 rev. *k revised december 3, 2013 2-mbit (128 k 16) static ram features very high speed: 55 ns wide voltage range: 1.65 v to 2.25 v pin compatible with cy62137cv18 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 5 ? a ultra low active power ? typical active current: 1.6 ma @ f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power byte power-down feature available in a pb-free 48-ball very fine-pitch ball grid package (vfbga) package functional description the cy62137fv18 is a high per formance cmos static ram organized as 128k words by 16 bits. this device features advanced circuit design to provid e ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high or both ble and bhe are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), both the byte high enable and the byte low enable are disabled (bhe , ble high), or during an active write operation (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from the memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. 128k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble bhe ble ce power down circuit logic block diagram
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 2 of 16 contents product portfolio .............................................................. 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 3 of 16 product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max cy62137fv18ll 1.65 1.8 2.25 55 1.6 2.5 13 18 1 5 pin configuration figure 1. 48-ball vfbga pinout [2, 3] we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc nc a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss top view notes 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 2. nc pins are not connected on the die. 3. pins d3, h1, g2, h6 and h3 in the vfbga package are address ex pansion pins for 4 mb, 8 mb, 16 mb, and 32 mb and 64 mb respect ively.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 4 of 16 maximum ratings exceeding maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential ....................................................?0.2 v to + 2.45 v dc voltage applied to outputs in high z state [4, 5] ......................................?0.2 v to 2.45 v dc input voltage [4, 5] ..................................?0.2 v to 2.45 v output current into outputs (low) ............................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................ > 2001 v latch up current .................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62137fv18 industrial ?40 c to +85 c 1.65 v to 2.25 v electrical characteristics over the operating range parameter description test conditions 55 ns unit min typ [7] max v oh output high voltage i oh = ?0.1 ma 1.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.2 v v ih input high voltage v cc = 1.65 v to 2.25 v 1.4 ? v cc + 0.2 v v il input low voltage v cc = 1.65 v to 2.25 v ?0.2 ? 0.4 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc(max) = 2.25 v i out = 0 ma cmos levels ?13 18 ma f = 1 mhz v cc(max) = 2.25 v ? 1.6 2.5 ma i sb1 [8] automatic power-down current ? cmos inputs ce > v cc ??? 0.2 v, or (bhe and ble ) > v cc ??? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe , we ) v cc(max) = 2.25 v ? 1 5 ? a i sb2 [8] automatic power-down current ? cmos inputs ce > v cc ? 0.2 v, or (bhe and ble ) > v cc ?? 0.2 v, v in > v cc ? 0.2 v, or v in < 0.2 v, f = 0 v cc(max) = 2.25 v ? 1 5 ? a notes 4. v il(min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih(max) =v cc + 0.5 v for pulse durations less than 20 ns. 6. full device ac operation assumes a minimum of 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c 8. chip enable (ce ) and byte enables (bhe and ble ) must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 5 of 16 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions 48-ball vfbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 ? c/w ? jc thermal resistance (junction to case) 10 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms v cc v cc output r2 30 pf gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output equivalent to: thvenin equivalent all input pulses r th r1 v including jig and scope parameters 1.80 v unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.80 v note 9. tested initially and after any design or process changes that may affect these parameters.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [11] data retention current v cc = 1.0 v, ce > v cc ? 0.2 v, or (bhe and ble ) > v cc ??? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?14 ? a t cdr [12] chip deselect to data retention time 0??ns t r [13] operation recovery time 55 ? ? ns data retention waveform figure 3. data retention waveform [14] v cc(min) v cc(min) t cdr v dr > 1.0 v data retention mode t r v cc ce or bhe .ble notes 10. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 11. chip enable (ce ) and byte enables (bhe and ble ) must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 12. tested initially and after any design or proce ss changes that may affect these parameters. 13. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 14. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling ch ip enable signals or by disabling both bhe and ble .
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 7 of 16 switching characteristics over the operating range parameter [15, 16] description 55 ns unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [17] 5 ? ns t hzoe oe high to high z [17, 18] ? 18 ns t lzce ce low to low z [17] 10 ? ns t hzce ce high to high z [17, 18] ? 18 ns t pu ce low to power up 0 ? ns t pd ce high to power down ? 55 ns t dbe ble /bhe low to data valid ? 55 ns t lzbe ble /bhe low to low z [17] 10 ? ns t hzbe ble /bhe high to high z [17, 18] ? 18 ns write cycle [19] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [17, 18] ? 18 ns t lzwe we high to low z [17] 10 ? ns notes 15. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1v/ns or less, timing re ference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the figure 2 on page 5 . 16. in an earlier revision of this device, under a specific application condition, read operations were limited to switching of the byte enable and/or chip enable signals as described in the application notes an13842 and an66311 . however, the issue has been fixed and in production now, and hence, these application notes are no longer applicable. they are available for download on our websit e as they contain information on the date code of the parts, be yond which the fix has been in production. 17. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 18. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state 19. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inac tive. the data input setup and hold timing should be referenced to the edge of the s ignal that terminates the write.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 8 of 16 switching waveforms figure 4. read cycle no.1 (address transition controlled) [20, 21] figure 5. read cycle no. 2 (oe controlled) [21, 22] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 20. the device is continuously selected. oe , ce = v il , bhe and/or ble = v il . 21. we is high for read cycle. 22. address valid before or similar to ce and bhe , ble transition low.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 9 of 16 figure 6. write cycle no. 1 (we controlled) [23, 24] figure 7. write cycle no. 2 (ce controlled) [23, 24] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 25 t bw t sce data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe /ble note 25 notes 23. data i/o is high impedance if oe = v ih . 24. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 25. during this period, the i/os are in output state. do not apply input signals.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 10 of 16 figure 8. write cycle no. 3 (we controlled) [26] figure 9. write cycle no. 4 (bhe /ble controlled, oe low) [26] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 27 ce address we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 27 data i/o address ce we bhe /ble notes 26. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 27. during this period, the i/os are in output state. do not apply input signals.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 11 of 16 truth table ce we oe bhe ble inputs or outputs mode power hxxx [28] x [28] high z deselect or power down standby (i sb ) x [28] x x h h high z deselect or power down standby (i sb ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) lhlhldata out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) note 28. the ?x? (don?t care) state for the chip enable (ce ) and byte enables (bhe and ble ) in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 12 of 16 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 55 CY62137FV18LL-55BVXI 51-85150 48-ball vfbga (pb-free) industrial contact your local cypress sales repres entative for availability of other parts. temperature grade: i = industrial pb-free package type: bv = 48-ball vfbga speed grade: 55 ns low power voltage range: 1.8 v typical process technology: 90 nm bus width = 16 density = 2-mbit family code: mobl sram family company id: cy = cypress cy -bv 621 3 7 f ll i 55 x v18
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 13 of 16 package diagram figure 10. 48-ball vfbga (6 8 1 mm) bv48/bz48 package outline, 51-85150 51-85150 *h
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 14 of 16 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy62137fv18 mobl ? document number: 001-08030 rev. *k page 15 of 16 document history page document title: cy62137fv18 mobl ? , 2-mbit (128 k 16) static ram document number: 001-08030 rev. ecn no. submission date orig. of change description of change ** 463660 see ecn nxr new data sheet. *a 469180 see ecn nsi minor change: moved to external web *b 569125 see ecn nxr converted from preliminary to final replaced 45 ns speed bin with 55 ns speed bin changed the i cc(max) value from 2.25 ma to 2.5 ma for test condition f=1 mhz changed the i sb2(typ) value from 0.5 ? a to 1 ? a changed the i sb2(max) value from 2.5 ? a to 5 ? a changed the i ccdr(typ) value from 0.5 ? a to 1 ? a and i ccdr(max) value from 2.5 ? a to 4 ? a *c 869500 see ecn vkn added footnote #12 related to t ace *d 908120 see ecn vkn added footnote #8 related to i sb2 and i ccdr made footnote #13 applicable to ac parameters from t ace changed t wc specification from 45 ns to 55 ns changed t sce , t aw , t pwe , t bw specification from 35 ns to 40 ns changed t hzwe specification from 18 ns to 20 ns *e 1274728 see ecn vkn/aesa changed t wc specification from 55 ns to 45 ns changed t sce , t aw , t pwe , t bw specification from 40 ns to 35 ns changed t hzwe specification from 20 ns to 18 ns *f 2943752 06/03/2010 vkn added contents added footnote related to chip enable and byte enables in truth table updated package diagram added sales, solutions, and legal information *g 3055165 10/12/2010 rame added contents added acronyms and units of measure update package diagram from *e to *f added ordering code definitions details. changed i sb1 /i sb2 /i ccdr test conditions to reflec t byte power down feature *h 3061313 10/15/2010 rame minor changes: corrected ce to ce and we to we in figures 7 and 8 *i 3263825 06/17/2011 rame replaced ce and oe with ce and oe in all instances in page 1. updated functional description (removed ?for best practice recommenda- tions, refer to the cypress applicati on note an1064, sram system guide- lines.?). updated in new template. *j 4102185 08/22/2013 vini updated switching characteristics : updated note 16. updated package diagram : spec 51-85150 ? changed revision from *f to *h. updated in new template. *k 4208614 12/03/2013 memj updated features : removed repeated instance of ?ultra low standby power?. completing sunset review.
document number: 001-08030 rev. *k revised december 3, 2013 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62137fv18 mobl ? ? cypress semiconductor corporation, 2006-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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